An integrated memory is an integrated circuit comprising an actual memory section called a memory cell formed of several electrically interconnected memory points, as well as peripheral circuits serving to control the memory points.
The sole object of the invention is to produce the actual memory section.
The most modern memory cells allowing for the storing of 10 bits have surface areas of from 20 to 25 .mu.m2 in 1.2 .mu.m technology, namely in which the smallest tapes and spaces measure 1.2 .mu.m. The surface area of a memory is thus about 14 to 17 times that of the elementary square of a lithograph (1200.times.1200 nm2).
FIG. 1 diagrammatically shows a perspective view of a known EPROM type memory cell, namely a memory cell electrically programmable solely on reading and erasable by ultraviolet radiation.
As represented on FIG. 1, a memory point is formed of a transistor comprising a source 4, a channel 5 and a drain 6, all embodied in a monocrystalline silicon semi-conductive substrate 8; the source and the drain present conductivities opposite those of the substrate.
The transistor also includes a grid nonconductor 10, generally silicon oxide, on which stacked are a first grid 12 and a second grid 14, both generally made of polycrystalline silicon doped with phosphorus. These two grids are separated by a fine insulating layer 16 generally made of silicon oxide.
The first grid 12 is a floating gate and the second grid 14 is the control grid of the memory point.
The memory point is electrically insulated from the other memory points and the peripheral control circuits of this point by means of a field oxide 18 embodied, for example, by the localized and superficial oxidation of the substrate through a mask of silicon nitride.
The entire memory cell is covered with a thick insulating layer 22, usually made of silicon oxide, in which the electric contact holes of the sources and drains, such as 24, are embodied. The electric connections between the sources and drains of the various memory points and/or the various peripheral control circuits are ensured by a conductive layer 26, generally made of aluminium and deposited on the nonconductive layer 22 and suitably engraved.
The electric connections between the control grids of the various memory points are defined at the same time as the control grids 14 and in the same polycrystalline silicon layer.
The applicant has encountered several technical problems in embodying these memory cells.
The first problem relates to integration density.
In fact, efforts are increasingly centered on finding a way to reduce the size of integrated circuits and especially of memories so as to increase their integration density. In currently known memories, efforts to resolve this problem have so far been centered solely on two factors for limiting reduction of the dimensions of the memory cell.
The first factor is the overlapping between the floating gate 12 and the field oxide 18; an overflowing X1 of the floating gate 12 above the field oxide 18 and an overflowing Y1 of the field oxide 18 with respect to the floating gate 12 are necessary owing to the inaccuracy of superimposing the various layers constituting the memory points and lithograph masks required for etching the various layers. These overflowings are respectively in the direction X of the lines of words (or grid connections) of the memory cell and in the direction Y of the channels of the memory points, said direction Y being perpendicular to the direction X.
The second factor is the need to provide insulating guards around the contact holes of the line of bits, namely around the contact holes of the drains of the memory points. One insulating guard X2 is provided in the direction X between the drain contact and the field oxide 18 and another insulating guard Y2 is provided in the direction Y between the drain contact and the grids 12 and 14.
As reduction of the lithographic dimensions is not generally accompanied by any proportional improvement as regards the accuracy of superpositions of different levels, especially of lithographic masks, the limitation factors mentioned above prove to be increasingly inhibitive as regards increasing the integration density of the memories.
Accordingly, a search is made to improve the methods for producing memory cells so as to obtain self-aligning or self-positioning in order to avoid overlapping between the floating gate and the field oxide and/or the insulating guards around the contact holes.
The second problem resides in the fact that the memory cells produced by conventional methods have small points marked by the reference P on FIG. 1. These points are localized at the level of the angles formed by the extreme edges of the grids and the interpoly nonconductor 16.
The third problem resides in the fact that the memory cells embodied by conventional methods have a structure which presents a large relief when it would be preferable to obtain a structure approximating a flat structure.